Liquid crystal display devices have advantages of being thin and consuming lower power, and therefore are in wide use in various fields. Especially, active matrix liquid crystal display devices including a switching element such as a thin film transistor (TFT) or the like for each of pixels provides a high level of performance owing to a high contrast ratio and an excellent response characteristic, and therefore are used for TV, monitors, notebook computers, and the like. Recently, the market scale of the active matrix liquid crystal display devices has been rapidly expanded.
Large-size liquid crystal display devices are used as display devices for amusement facilities, information displays, digital signage devices and the like. Along with the expansion of such uses, it has been attempted to provide pseudo realization of a large-screen display device by arraying a plurality of liquid crystal display devices (occasionally referred to as “tiling technology”). Such a structure is referred to as a “multi-display system” or the like and is a target of attention as a system for realizing a high-precision large screen.
A liquid crystal display device is driven by a line sequential system. According to the line sequential system, scanning is performed in a line sequential manner from the top to the bottom of a liquid crystal panel. In an active matrix liquid crystal display device, in one vertical scanning period, TFTs are turned ON on a pixel row-by-pixel row basis by a scanning line provided for each of pixel rows, and a voltage is written to pixels on a pixel row-by-pixel row basis.
FIG. 28(a) shows an equivalent circuit of a conventionally common active matrix liquid crystal display device 700. As shown in FIG. 28(a), in the liquid crystal display device 700, a TFT 712 is provided for each of a plurality of pixels 701 located in a matrix. A gate electrode of the TFT 712 is connected to a scanning line 700g provided for each of pixel rows, and a source electrode of the TFT 712 is connected to a signal line 700s provided for each of pixel columns. A drain electrode of the TFT 712 is connected to a pixel electrode 711 provided for each of the pixels 701.
FIG. 28(b) shows waveforms of a scanning signal voltage supplied from the scanning lines 700g to the TFTs 712. FIG. 28(b) corresponds to FIG. 28(a) and shows the waveforms of the scanning signal voltage supplied from the scanning lines 700g provided for a first pixel row, a second pixel row, a third pixel row and a final pixel row. As shown in FIG. 28(b), the scanning signal voltage becomes a gate ON voltage sequentially from the first pixel row. Therefore, the timing to write a voltage to the pixels 701 varies in accordance with the pixel row. The time lag between the first pixel row (i.e., the uppermost pixel row) and the final row (i.e., the lowermost pixel row) is a time period corresponding to approximately one vertical scanning period (one frame) (i.e., about 16.7 ms in the case where the driving is performed at 60 Hz).
As can be seen, the timing to write a voltage to the pixels 701, namely, the timing at which the pixel data is rewritten and the display is switched is gradually shifted from the top to the bottom of a liquid crystal panel. Therefore, the following problem may occur when a video showing motions is displayed.
FIG. 29(a) shows a vertical bar (band extending in a top-bottom direction) 70 displayed in a still manner on a screen of the liquid crystal display device 700, and FIG. 29(b) shows the vertical bar 70 displayed in a scroll manner so as to move rightward on the screen of the liquid crystal display device 700. In the case of the still display, as shown in FIG. 29(a), the vertical bar 70 is displayed parallel to the top-bottom direction, namely, normally. By contrast, in the case of the scroll display, as shown in FIG. 29(b), the vertical bar 70 is displayed as being inclined with respect to the top-bottom direction.
FIG. 30(a) shows the vertical bar 70 displayed in a still manner on a screen of a multi-display system 800, and FIG. 30(b) shows the vertical bar 70 displayed in a scroll manner so as to move rightward on the screen of the multi-display system 800. The multi-display system 800 shown in FIGS. 30(a) and 30(b) includes 12 liquid crystal display devices 700 arrayed in three rows by four columns. In the case of the still display, as shown in FIG. 30(a), in each liquid crystal display device 700 and also in the entire multi-display system 800, the vertical bar 70 is displayed parallel to the top-bottom direction, namely, normally. By contrast, in the case of the scroll display, as shown in FIG. 30(b), in each liquid crystal display device 700 and also in the entire multi-display system 800, the vertical bar 70 is displayed as being inclined with respect to the top-bottom direction. In addition, the inclined vertical bar 70 is discontinuous between the liquid crystal display devices 700 adjacent to each other in the top-bottom direction. Herein, the term “discontinuous” does not indicate that the vertical bar 70 is not displayed in a frame area, but indicates that parts of the vertical bar 70 displayed by the liquid crystal display devices 700 are not located on a strictly straight line (namely, that the parts of the vertical bar 70 are displayed in a state of being shifted in a left-right direction).
According to a conventionally known technique, a frame memory for storing image data is provided in each of a plurality of liquid crystal display devices included in a multi-display system, and for a liquid crystal display device located in the second and subsequent rows, display is provided in a delayed manner. In this way, the continuity of the display is kept.
This technique can solve the discontinuity of the display between the liquid crystal display devices, but cannot solve the inclination of the display in each of the liquid crystal display devices. This technique also requires a frame memory for each of the liquid crystal display devices, and thus raises the production cost. In addition, when the number of the liquid crystal display devices included in the multi-display system is increased and thus the number of the liquid crystal display devices located in a column direction is increased (namely, when the number of the liquid crystal display device rows is increased), the display needs to be delayed in correspondence with the number of the liquid crystal display device rows. In the case where, for example, the liquid crystal display devices are arrayed in three columns as shown in FIG. 30(b), the display on the liquid crystal display devices on the third row (i.e., the lowermost row) needs to be delayed by two vertical scanning periods with respect to the display on the liquid crystal display devices on the first row (i.e., the uppermost row). In a liquid crystal display device, for which the display is delayed by a long time period, the frame memory needs to have a larger capacity in correspondence with the delay. This further raises the production cost.
Patent Document 1 discloses a liquid crystal display device capable of writing a voltage to all the pixels globally. FIG. 31 shows a liquid crystal display device 900 disclosed in Patent Document 1.
As shown in FIG. 31, the liquid crystal display device 900 includes a plurality of pixels 901 arrayed in a matrix. A scanning line 900g1 and a scanning line 900g2 are provided for each of pixel rows, and a signal line 900s is provided for each of pixel columns. A storage capacitor line 900c1 and a temporary capacitor line 900c2 are provided for each of the pixel rows.
The plurality of pixels 901 are each provided with a liquid crystal element LC, a storage capacitor element 922A and a temporary capacitor element 922B. The liquid crystal element LC is a capacitor element formed by a pixel electrode for each pixel 901, a part of a counter electrode that faces the pixel electrode 901, and a part of a liquid crystal layer that is located between the pixel electrode and the counter electrode (none of these components is shown).
Each pixel 901 is provided with two TFT elements 912A and 912B. Among the two TFT elements 912A and 912B, the TFT element 912A is a switching element for switching a conductive state and a non-conductive state of the temporary capacitor element 922B and the liquid crystal element LC/the storage capacitor element 922A. A gate electrode of the TFT element 912A is connected to the scanning line 900g1, and a source electrode of the TFT element 912A is connected to an end of the temporary capacitor element 922B. A drain electrode of the TFT element 912A is connected to one end of the storage capacitor element 922A and also an end of the liquid crystal element LC (i.e., pixel electrode).
The other TFT element 912B is a switching element for switching a conductive state and a non-conductive state of the temporary capacitor element 922B and the signal line 900s. A gate electrode of the TFT element 912B is connected to the scanning line 900g2, and a source electrode of the TFT element 912B is connected to the signal line 900s. A drain electrode of the TFT element 912B is connected to one end of the temporary capacitor element 922B.
The storage capacitor element 922A is a capacitor element for storing an accumulated charge in the liquid crystal element LC stably. As described above, one end of the storage capacitor element 922A is connected to the drain electrode of the TFT element 912A. The other end of the storage capacitor element 922A is connected to the storage capacitor line 900c1.
The temporary capacitor element 922B is a capacitor element for temporarily storing a video voltage corresponding to a video signal before the video signal is written to the liquid crystal element LC. As described above, one end of the temporary capacitor element 922B is connected to the source electrode of the TFT element 912A and the drain electrode of the TFT element 912B. The other end of the temporary capacitor element 922B is connected to the temporary capacitor line 900c2.
In the liquid crystal display device 900 having the above-described structure, in one vertical scanning period, first, video signals are sequentially supplied to the temporary capacitor elements 922B in a line sequential manner and temporarily stored in the capacitor elements 922B. Then, the video signals are transferred (written) to the liquid crystal elements LC and the storage capacitor elements 922A in all the pixels 901 globally.